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| M54HC573 RAD-HARD OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s s s HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 573 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9202-072 DILC-20 FPC-20 ORDER CODES PACKAGE DILC FPC FM M54HC573D M54HC573K EM M54HC573D1 M54HC573K1 DESCRIPTION The M54HC573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). PIN CONNECTION While the LE input is held at a high level, the Q outputs will follow the data input precisely. When LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while is at high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. May 2004 Rev. 1 1/12 M54HC573 Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin Description PIN N 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs 3 State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage Table 2: Truth Table INPUTS OE H L L L LE X L H H D X X L H OUTPUTS Q Z NO CHANGE (*) L H X: Don't Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. 2/12 M54HC573 Figure 3: Logic Diagram Table 3: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 35 70 420 -65 to +150 265 Unit V V V mA mA mA mA mW C C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 4: Recommended Operating Conditions Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns 3/12 M54HC573 Table 5: DC Specifications Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-6.0 mA IO=-7.8 mA IO=20 A IO=20 A IO=20 A IO=6.0 mA IO=7.8 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.5 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 5 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 10 80 A A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH ICC 4/12 M54HC573 Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) TA = 25C Min. Typ. 25 7 6 50 15 13 60 20 17 42 14 12 57 19 16 55 17 14 66 22 19 40 17 15 40 8 7 16 5 3 Max. 60 12 10 115 23 20 155 31 26 110 22 19 150 30 26 140 28 24 180 36 31 125 25 21 75 15 13 50 10 9 5 5 5 Value -40 to 85C Min. Max. 75 15 13 145 29 25 195 39 33 140 28 24 190 38 32 175 35 30 225 45 38 155 31 26 95 19 16 65 13 11 5 5 5 -55 to 125C Min. Max. 90 18 15 175 35 30 235 47 40 165 33 28 225 45 38 210 42 36 270 54 46 190 38 32 110 22 19 75 15 13 5 5 5 ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (LE - Q) 50 50 ns 150 ns tPLH tPHL Propagation Delay Time (D - Q) 50 ns 150 ns tPZL tPZH High Impedance Output Enable Time 50 RL = 1 K ns 150 RL = 1 K ns tPLZ tPHZ High Impedance Output Disable Time tW(L) tW(H) ts Minimum Pulse Width Minimum Set-up Time Minimum Hold Time 50 RL = 1 K ns 50 ns 50 ns th 50 ns 5/12 M54HC573 Table 7: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 5 10 51 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 33 + 18 x n (pF) Figure 4: Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50) SWITCH Open VCC GND 6/12 M54HC573 Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimum Pulse Width, Dn To LE Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 7/12 M54HC573 Figure 7: Waveform - Propagation Delay Times (f=1MHz; 50% duty cycle) 8/12 M54HC573 DILC-20 MECHANICAL DATA mm. DIM. MIN. A a1 a2 B b b1 D E e e1 e2 F I K L 11.30 1.14 1.27 22.73 7.62 7.29 2.1 3.00 0.63 1.93 0.40 0.20 25.14 7.36 0.88 2.03 0.45 0.254 25.40 7.62 2.54 22.86 7.87 7.49 22.99 8.12 7.70 3.86 11.56 1.40 0.445 0.045 0.050 0.895 0.300 0.287 TYP MAX. 2.71 3.70 1.14 2.23 0.50 0.30 25.65 7.87 MIN. 0.083 0.118 0.025 0.076 0.016 0.008 0.990 0.290 0.035 0.080 0.018 0.010 1.000 0.300 0.100 0.900 0.310 0.295 0.905 0.320 0.303 0.152 0.455 0.055 TYP. MAX. 0.107 0.146 0.045 0.088 0.020 0.012 1.010 0.310 inch 0016178J 9/12 M54HC573 FPC-20 MECHANICAL DATA mm. DIM. MIN. A B C D E F G H L M N O P 1.14 0.10 0.38 7.24 24.46 0.45 0.50 7.87 1.27 0.18 1.40 0.25 0.045 0.004 9.98 9.98 1.45 0.10 11.30 TYP 10.16 10.16 1.61 0.127 11.43 1.27 0.43 0.48 8.16 26.67 0.55 0.015 0.285 0.960 0.018 0.020 0.310 0.050 0.007 0.055 0.010 MAX. 10.34 10.34 1.78 0.18 11.56 MIN. 0.393 0.393 0.57 0.004 0.445 TYP. 0.400 0.400 0.63 0.005 0.450 0.050 0.017 0.019 0.320 1.050 0.022 MAX. 0.407 0.407 0.070 0.007 0.455 inch 016032F 10/12 M54HC573 Table 8: Revision History Date 14-May-2004 Revision 1 First Release Description of Changes 11/12 M54HC573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 12/12 |
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